MAX5965AEAX+【PDF 26/54 页】IC PSE CTRLR FOR POE 36SSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录43

22页 23页 24页 25页 [26页]27页 28页 29页 30页

High-Power, Quad, Monolithic, PSE Controllers

for Power over Ethernet

26 ______________________________________________________________________________________

Figure 9. Slave Address

SDAIN/SDA

SCL

MSB

LSB

ACK

R/W

Figure 10. Control Byte Received

SLAVE ADDRESS

CONTROL BYTE

ACKNOWLEDGE FROM THE MAX5965A/MAX5965B

D15 D14 D13 D12 D11 D10 D9 D8

CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION

R/W

Slave Address

The MAX5965A/MAX5965B have a 7-bit long slave

address (Figure 9). The bit following the 7-bit slave

address (bit eight) is the R/W bit, which is low for a

write command and high for a read command.

010 always represents the first 3 bits (MSBs) of the

MAX5965A/MAX5965B slave address. Slave address

bits A3, A2, A1, and A0 represent the states of the

MAX5965A/MAX5965Bs A3, A2, A1, and A0 inputs,

allowing up to sixteen MAX5965A/MAX5965B devices

to share the bus. The states of the A3, A2, A1, and A0

latch in upon the reset of the MAX5965A/MAX5965B

into register R11h. The MAX5965A/MAX5965B monitor

the bus continuously, waiting for a START condition fol-

lowed by the MAX5965A/MAX5965Bs slave address.

When a MAX5965A/MAX5965B recognizes its slave

address, the MAX5965A/MAX5965B acknowledge and

are then ready for continued communication.

Global Addressing and Alert Response Protocol

The global address call is used in writing mode to write

the same register to multiple devices (address 0x60). In

read mode (address 0x61), the global address call is

used as the alert response address. When responding

to a global call, the MAX5965A/MAX5965B put their

own address out on the data line whenever the interrupt

is active. Every other device connected to the SDAOUT

line that has an active interrupt also does this. After

every bit transmitted, the MAX5965A/MAX5965B check

that the data line effectively corresponds to the data it

is delivering. If it is not, it then backs off and frees the

data line. This litigation protocol always allows the part

with the lowest address to complete the transmission.

The microcontroller can then respond to the interrupt

and take proper actions. The MAX5965A/MAX5965B do

not reset their own interrupt at the end of the alert

response protocol. The microcontroller has to do it by

clearing the event register through their CoR adresses

or activating the CLR_INT pushbutton.

Message Format for Writing to the

MAX5965A/MAX5965B

A write to the MAX5965A/MAX5965B comprises of the

MAX5965A/MAX5965Bs slave address transmission

with the R/W bit set to 0, followed by at least 1 byte of

information. The first byte of information is the com-

mand byte (Figure 10). The command byte determines

which register of the MAX5965A/MAX5965B is written to

by the next byte, if received. If the MAX5965A/

MAX5965B detect a STOP condition after receiving the

command byte, the MAX5965A/MAX5965B take no fur-

ther action beyond storing the command byte. Any

bytes received after the command byte are data bytes.

The first data byte goes into the internal register of the

MAX5965A/MAX5965B selected by the command byte.

If the MAX5965A/MAX5965B transmit multiple data

bytes before the MAX5965A/MAX5965B detect a STOP

condition, these bytes store in subsequent MAX5965A/

MAX5965B internal registers because the control byte

address autoincrements.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式